1. Field of the Present Invention
The present invention generally relates to the field of data processing systems and more particularly to an electronic system enabled for dynamic test verification of interconnections among various devices such as integrated circuits on a printed circuit board.
2. History of Related Art
A printed circuit board of any significant complexity may include a large number of integrated circuits, each of which has many input/output signals. In addition, an electronic system may include multiple interconnected circuit boards, each of which has its own set of integrated circuits. As the number of integrated circuits increases and the number of signals per integrated circuit increases, the number of interconnecting signals increases dramatically. With a very large number of signals propagating between the various integrated circuits, the task of testing a printed circuit board for proper interconnections among the various integrated circuits becomes exceedingly complex. Typically, verification of the interconnections is achieved using complex and expensive test machinery that is capable of driving a large number of inputs at high speed with a predetermined pattern or sequence of patterns while simultaneously monitoring a large number of output signals. When test equipment of this type is not available, existing methods such as conventional boundary scan methods provide an economical procedure for checking various functions of the system. Boundary scan methods, however, typically implement some form of serial communication bus operating at a clock speed that is significantly slower than the clock speed at which the system will ultimately operate. Thus, conventional boundary scan methods are suitable for testing gross functionality of a system or device under relaxed timing conditions. Because, however, various system characteristics, such as stray capacitance, may not exhibit themselves at relaxed timing conditions, it would be highly desirable to expand the testing enabled by conventional boundary scan techniques to encompass clock speeds that the system and its components will experience in the field.
The problems identified above are addressed by a system, device, and method for dynamically testing integrated circuits. The system includes a first integrated circuit including input pins, output pins, normal operating logic, and control logic. The control logic is connectable to the input pins and configured to initiate a test interval based on a state of the input pins and to record the state of the input pins during the test interval. A second integrated circuit of the system includes input pins, output pins, normal operating logic, and test control logic. The control logic connectable to the output pins and configured to generate a user programmable set of test output signals. At least some of the output pins of the second integrated circuit are connected to at least some of the input pins of the first integrated circuit. The test control logic of the first integrated may be configured to initiate the test interval when the state of the input pins matches a predefined state. A portion of the test control logic of the first and second devices may be driven by a system clock that drives the operating logic such that the test output signals of the second device and the test input signals of the first device transition at the frequency of the system clock during the test interval. The test output signals may transition among one of a set of possible test output states, wherein the possible test output states include a predetermined pattern, an inverse of the predetermined pattern, an all 0""s pattern, and an all 1""s pattern.